MC9S12G Datasheet, PDF (469/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Chapter 15
Digital Analog Converter (DAC_8B5V)
15.1 Revision History
Table 15-1. Revision History Table
Rev. No.
(Item No.)
Data
0.1 28-Oct.-09
0.4 28-Oct.-09 (Thomas Becker)
0.5 12-Nov.-09 (Thomas Becker)
0.6 17-Nov.-09 (Thomas Becker)
0.7 18-Nov.-09 (Thomas Becker)
0.8 04-Dec.-09 (Thomas Becker)
0.9 05-Jan.-10 (Thomas Becker)
0.91 13-Jan.-10 (Thomas Becker)
0.92 12-Feb.-10 (Thomas Becker)
1.0 12-Apr.-10
1.01 04-May-10,
1.02 12-May-10
1.1 25-May-10
1.2 25-Jun.-10
1.3 29-Jul.-10
1.4 17-Nov.-10
Sections
Affected
Substantial Change(s)
all
Initial Version
all
Initial Version
all
Reworked all sections, renamed pin names
1.2.4
Added CPU stop mode
1.2, 1.3
Update block diagram, removed analog and digital submodule,
added section 1.3
1.4.2
- changed reset value of FVR bit to 1’b1
- added new bit “Load” to DACCTL register
- removed S3 switch description
1.3, 1.4.2.1, 1.5 - renamed register bit “Load” to “Drive”, request by analog team
- renamed pin DAC to DACU
1.4.2.3
- added debug register
all
- fixed typo
1.4.2.1
Added DACCTL register bit DACDIEN
Table 1.2,
Section 1.4
Replaced VRL,VRL with variable
correct wrong figure, table numbering
Section 1.4
replaced ipt_test_mode with ips_test_access
new description/address of DACDEBUG register
15.4.2.1
Removed DACCTL register bit DACDIEN
15.4
Correct table and figure title format
15.2
Fixed typos
15.2.2
Update the behavior of the DACU pin during stop mode
Glossary
Table 15-2. Terminology
Term
DAC
VRL
Digital to Analog Converter
Low Reference Voltage
Meaning
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
469
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.