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MC9S12G Datasheet, PDF (606/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Serial Peripheral Interface (S12SPIV5)
19.2.2 MISO â Master In/Slave Out Pin
This pin is used to transmit data out of the SPI module when it is conï¬gured as a slave and receive data
when it is conï¬gured as master.
19.2.3 SS â Slave Select Pin
This pin is used to output the select signal from the SPI module to another peripheral with which a data
transfer is to take place when it is conï¬gured as a master and it is used as an input to receive the slave select
signal when the SPI is conï¬gured as slave.
19.2.4 SCK â Serial Clock Pin
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
19.3 Memory Map and Register Deï¬nition
This section provides a detailed description of address space and registers used by the SPI.
19.3.1 Module Memory Map
The memory map for the SPI is given in Figure 19-2. The address listed for each register is the sum of a
base address and an address offset. The base address is deï¬ned at the SoC level and the address offset is
deï¬ned at the module level. Reads from the reserved bits return zeros and writes to the reserved bits have
no effect.
Register
Name
Bit 7
SPICR1 R
SPIE
W
SPICR2 R
0
W
SPIBR
R
0
W
SPISR
R SPIF
W
SPIDRH R R15
W T15
6
SPE
XFRW
SPPR2
0
5
4
3
SPTIE
MSTR
CPOL
0
MODFEN BIDIROE
0
SPPR1
SPPR0
SPTEF
MODF
0
R14
R13
R12
R11
T14
T13
T12
T11
= Unimplemented or Reserved
Figure 19-2. SPI Register Summary
2
CPHA
0
SPR2
0
R10
T10
1
SSOE
SPISWAI
SPR1
0
R9
T9
Bit 0
LSBFE
SPC0
SPR0
0
R8
T8
MC9S12G Family Reference Manual, Rev.1.01
606
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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