MC9S12G Datasheet, PDF (255/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Chapter 7
Background Debug Module (S12SBDMV1)
Table 7-1. Revision History
Revision Number
Date
1.03
14.May.2009
1.04
30.Nov.2009
1.05
07.Dec.2010
1.06
02.Mar.2011
Sections
Affected
7.3.2.2/7-261
7.2/7-257
Summary of Changes
Internal Conditional text only
Internal Conditional text only
Standardized format of revision history table header.
Corrected BPAE bit description.
Removed references to fixed VCO frequencies
7.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
• TAGGO command not supported by S12SBDM
• External instruction tagging feature is part of the DBG module
• S12SBDM register map and register content modified
• Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
• Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
7.1.1 Features
The BDM includes these distinctive features:
• Single-wire communication with host development system
• Enhanced capability for allowing more flexibility in clock rates
• SYNC command to determine communication rate
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
255
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.