MC9S12G Datasheet, PDF (473/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Digital Analog Converter (DAC_8B5V)
15.4.2.1 Control Register (DACCTL)
)
Module Base + 0x0000
R
W
Reset
7
FVR
1
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
DRIVE
0
0
0
0
0
= Unimplemented
Figure 15-3. Control Register (DACCTL)
Access: User read/write¹
1
0
DACM[2:0]
0
0
Table 15-3. DACCTL Field Description
Field
Description
7
FVR
Full Voltage Range — This bit defines the voltage range of the DAC.
0 DAC resistor network operates with the reduced voltage range
1 DAC resistor network operates with the full voltage range
Note: For more details see Section 15.5.7, “Analog output voltage calculation”.
6
DRIVE
Drive Select — This bit selects the output drive capability of the operational amplifier, see electrical Spec. for
more details.
0 Low output drive for high resistive loads
1 High output drive for low resistive loads
2:0 Mode Select — These bits define the mode of the DAC. A write access with an unsupported mode will be ignored.
DACM[2:0] 000 Off
001 Operational Amplifier
100 Unbuffered DAC
101 Unbuffered DAC with Operational Amplifier
111 Buffered DAC
other Reserved
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
473
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.