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MC9S12G Datasheet, PDF (1116/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.
Electrical Characteristics
In Figure A-7 the timing diagram for master mode with transmission format CPHA=1 is depicted.
SS
(Output)
SCK
(CPOL = 0)
(Output)
SCK
(CPOL = 1)
(Output)
MISO
(Input)
1
2
4
4
5
6
MSB IN2
9
MOSI
(Output)
Port Data
Master MSB OUT2
12
12
Bit MSB-1. . . 1
11
Bit MSB-1. . . 1
13
3
13
LSB IN
Master LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1,bit 2... MSB.
Figure A-7. SPI Master Timing (CPHA = 1)
Port Data
MC9S12G Family Reference Manual, Rev.1.01
1116
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.