MC9S12G Datasheet, PDF (346/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
NOTE
A write to this register starts the RTI time-out period. A change of the
RTIOSCSEL bit (writing a different value or loosing UPOSC status)
re-starts the RTI time-out period.
Table 10-9. CPMURTI Field Descriptions
Field
Description
7
RTDEC
6–4
RTR[6:4]
3–0
RTR[3:0]
Decimal or Binary Divider Select Bit — RTDEC selects decimal or binary based prescaler values.
0 Binary based divider value. See Table 10-10
1 Decimal based divider value. See Table 10-11
Real Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See
Table 10-10 and Table 10-11.
Real Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity.Table 10-10 and Table 10-11 show all possible divide values selectable by the
CPMURTI register.
RTR[3:0]
0000 (÷1)
0001 (÷2)
0010 (÷3)
0011 (÷4)
0100 (÷5)
0101 (÷6)
0110 (÷7)
0111 (÷8)
1000 (÷9)
1001 (÷10)
1010 (÷11)
1011 (÷12)
1100 (÷13)
1101 (÷14)
Table 10-10. RTI Frequency Divide Rates for RTDEC = 0
000
(OFF)
OFF¹
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
001
(2¹⁰)
2¹⁰
2x2¹⁰
3x2¹⁰
4x2¹⁰
5x2¹⁰
6x2¹⁰
7x2¹⁰
8x2¹⁰
9x2¹⁰
10x2¹⁰
11x2¹⁰
12x2¹⁰
13x2¹⁰
14x2¹⁰
010
(2¹¹)
2¹¹
2x2¹¹
3x2¹¹
4x2¹¹
5x2¹¹
6x2¹¹
7x2¹¹
8x2¹¹
9x2¹¹
10x2¹¹
11x2¹¹
12x2¹¹
13x2¹¹
14x2¹¹
RTR[6:4] =
011
(2¹²)
2¹²
2x2¹²
3x2¹²
4x2¹²
5x2¹²
6x2¹²
7x2¹²
8x2¹²
9x2¹²
10x2¹²
11x2¹²
12x2¹²
13x2¹²
14x2¹²
100
(2¹³)
2¹³
2x2¹³
3x2¹³
4x2¹³
5x2¹³
6x2¹³
7x2¹³
8x2¹³
9x2¹³
10x2¹³
11x2¹³
12x2¹³
13x2¹³
14x2¹³
101
(2¹⁴)
2¹⁴
2x2¹⁴
3x2¹⁴
4x2¹⁴
5x2¹⁴
6x2¹⁴
7x2¹⁴
8x2¹⁴
9x2¹⁴
10x2¹⁴
11x2¹⁴
12x2¹⁴
13x2¹⁴
14x2¹⁴
110
(2¹⁵)
2¹⁵
2x2¹⁵
3x2¹⁵
4x2¹⁵
5x2¹⁵
6x2¹⁵
7x2¹⁵
8x2¹⁵
9x2¹⁵
10x2¹⁵
11x2¹⁵
12x2¹⁵
13x2¹⁵
14x2¹⁵
111
(2¹⁶)
2¹⁶
2x2¹⁶
3x2¹⁶
4x2¹⁶
5x2¹⁶
6x2¹⁶
7x2¹⁶
8x2¹⁶
9x2¹⁶
10x2¹⁶
11x2¹⁶
12x2¹⁶
13x2¹⁶
14x2¹⁶
MC9S12G Family Reference Manual, Rev.1.01
346
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.