MC9S12G Datasheet, PDF (335/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.2.7 VDD — Internal Regulator Output Supply (Core Logic)
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for
the core logic.
This supply domain is monitored by the Low Voltage Reset circuit.
10.2.8 VDDF — Internal Regulator Output Supply (NVM Logic)
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for
the NVM logic.
This supply domain is monitored by the Low Voltage Reset circuit
10.2.9 API_EXTCLK — API external clock output pin
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification
to which pin it connects.
10.3 Memory Map and Registers
This section provides a detailed description of all registers accessible in the S12CPMU.
10.3.1 Module Memory Map
The S12CPMU registers are shown in Figure 10-3.
Addres
s
0x0034
0x0035
0x0036
0x0037
0x0038
0x0039
0x003A
Name
CPMU
SYNR
CPMU
REFDIV
CPMU
POSTDIV
CPMUFLG
CPMUINT
CPMUCLKS
CPMUPLL
Bit 7
6
5
4
3
2
1
Bit 0
R
VCOFRQ[1:0]
W
R
REFFRQ[1:0]
W
0
0
R
0
0
0
W
R
RTIF
W
PORF
LVRF LOCKIF
R
0
RTIE
W
0
LOCKIE
R
PLLSEL
W
PSTP
0
COP
OSCSEL1
R
0
W
0
FM1
FM0
= Unimplemented or Reserved
SYNDIV[5:0]
REFDIV[3:0]
POSTDIV[4:0]
LOCK
ILAF
OSCIF
UPOSC
0
0
0
OSCIE
PRE
0
PCE
0
RTI
OSCSEL
0
COP
OSCSEL0
0
Figure 10-3. CPMU Register Summary
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
335
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.