MC9S12G Datasheet, PDF (482/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.1.1 Glossary
ACK
CAN
CRC
EOF
FIFO
IFS
SOF
CPU bus
CAN bus
oscillator clock
bus clock
CAN clock
Table 16-2. Terminology
Acknowledge of CAN message
Controller Area Network
Cyclic Redundancy Code
End of Frame
First-In-First-Out Memory
Inter-Frame Sequence
Start of Frame
CPU related read/write data bus
CAN protocol related serial bus
Direct clock from external oscillator
CPU bus related clock
CAN protocol related clock
16.1.2 Block Diagram
Oscillator Clock
Bus Clock
MSCAN
CANCLK
Tq Clk
MUX
Presc.
Receive/
Transmit
Engine
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Control
and
Status
Configuration
Registers
Message
Filtering
and
Buffering
Wake-Up
Low Pass Filter
Figure 16-1. MSCAN Block Diagram
RXCAN
TXCAN
MC9S12G Family Reference Manual, Rev.1.01
482
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.