MC9S12G Datasheet, PDF (641/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Timer Module (TIM16B8CV3)
Table 20-6. TSCR1 Field Descriptions
Field
7
TEN
6
TSWAI
5
TSFRZ
4
TFFCA
3
PRNT
Description
Timer Enable
0 Disables the main timer, including the counter. Can be used for reducing power consumption.
1 Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator because the ÷64 is
generated by the timer prescaler.
Timer Module Stops While in Wait
0 Allows the timer module to continue running during wait.
1 Disables the timer module when the MCU is in the wait mode. Timer interrupts cannot be used to get the MCU
out of wait.
TSWAI also affects pulse accumulator.
Timer Stops While in Freeze Mode
0 Allows the timer counter to continue running while in freeze mode.
1 Disables the timer counter whenever the MCU is in freeze mode. This is useful for emulation.
TSFRZ does not stop the pulse accumulator.
Timer Fast Flag Clear All
0 Allows the timer flag clearing to function normally.
1 For TFLG1(0x000E), a read from an input capture or a write to the output compare channel (0x0010–0x001F)
causes the corresponding channel flag, CnF, to be cleared. For TFLG2 (0x000F), any access to the TCNT
register (0x0004, 0x0005) clears the TOF flag. Any access to the PACNT registers (0x0022, 0x0023) clears
the PAOVF and PAIF flags in the PAFLG register (0x0021) if channel 7 exists. This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid accidental flag
clearing due to unintended accesses.
Precision Timer
0 Enables legacy timer. PR0, PR1, and PR2 bits of the TSCR2 register are used for timer counter prescaler
selection.
1 Enables precision timer. All bits of the PTPSR register are used for Precision Timer Prescaler Selection, and
all bits.
This bit is writable only once out of reset.
20.3.2.7 Timer Toggle On Overflow Register 1 (TTOV)
R
W
Reset
7
TOV7
0
Read: Anytime
Write: Anytime
6
TOV6
5
TOV5
4
TOV4
3
TOV3
2
TOV2
1
TOV1
0
0
0
0
0
0
Figure 20-13. Timer Toggle On Overflow Register 1 (TTOV)
0
TOV0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
641
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.