MC9S12G Datasheet, PDF (315/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

8.5.2 Scenario 1
A trigger is generated if a given sequence of 3 code events is executed.
Figure 8-27. Scenario 1
SCR1=0011
SCR2=0010
State1
M1
State2
M2
SCR3=0111
M0
State3
S12S Debug Module (S12SDBG)
Final State
Scenario 1 is possible with S12SDBGV1 SCR encoding
8.5.3 Scenario 2
A trigger is generated if a given sequence of 2 code events is executed.
Figure 8-28. Scenario 2a
SCR1=0011
SCR2=0101
State1
M1
State2
M2
Final State
A trigger is generated if a given sequence of 2 code events is executed, whereby the first event is entry into
a range (COMPA,COMPB configured for range mode). M1 is disabled in range modes.
Figure 8-29. Scenario 2b
SCR1=0111
SCR2=0101
State1
M01 _State2
M2
Final State
A trigger is generated if a given sequence of 2 code events is executed, whereby the second event is entry
into a range (COMPA,COMPB configured for range mode)
Figure 8-30. Scenario 2c
SCR1=0010
SCR2=0011
State1
M2
State2
M0
Final State
All 3 scenarios 2a,2b,2c are possible with the S12SDBGV1 SCR encoding
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
315
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.