MC9S12G Datasheet, PDF (34/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Device Overview MC9S12G-Family
• Bus-off recovery by software intervention or automatically
• 16-bit time stamp of transmitted/received messages
1.3.12 Serial Communication Interface Module (SCI)
• Up to three SCI modules
• Full-duplex or single-wire operation
• Standard mark/space non-return-to-zero (NRZ) format
• Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with programmable pulse widths
• 13-bit baud rate selection
• Programmable character length
• Programmable polarity for transmitter and receiver
• Active edge receive wakeup
• Break detect and transmit collision detect supporting LIN 1.3, 2.0, 2.1 and SAE J2602
1.3.13 Serial Peripheral Interface Module (SPI)
• Up to three SPI modules
• Configurable 8- or 16-bit data size
• Full-duplex or single-wire bidirectional
• Double-buffered transmit and receive
• Master or slave mode
• MSB-first or LSB-first shifting
• Serial clock phase and polarity options
1.3.14 Analog-to-Digital Converter Module (ADC)
Up to 16-channel, 10-bit/12-bit¹ analog-to-digital converter
— 3 us conversion time
— 8-/10¹-bit resolution
— Left or right justified result data
— Wakeup from low power modes on analog comparison > or <= match
— Continuous conversion mode
— External triggers to initiate conversions via GPIO or peripheral outputs such as PWM or TIM
— Multiple channel scans
— Precision fixed voltage reference for ADC conversions
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• Pins can also be used as digital I/O including wakeup capability
1. 12-bit resolution only available on S12GA192 and S12GA240 devices.
MC9S12G Family Reference Manual, Rev.1.01
34
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.