MC9S12G Datasheet, PDF (354/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
10.3.2.15 Autonomous Clock Trimming Register (CPMUACLKTR)
The CPMUACLKTR register configures the trimming of the Autonomous Clock (ACLK - trimmable
internal RC-Oscillator) which can be selected as clock source for some CPMU features.
0x02F3
7
6
5
4
3
2
1
0
R
0
0
ACLKTR5 ACLKTR4 ACLKTR3 ACLKTR2 ACLKTR1 ACLKTR0
W
Reset
F
F
F
F
F
F
0
0
After de-assert of System Reset a value is automatically loaded from the Flash memory.
Figure 10-19. Autonomous Periodical Interrupt Trimming Register (CPMUACLKTR)
Read: Anytime
Write: Anytime
Table 10-17. CPMUACLKTR Field Descriptions
Field
Description
7–2
Autonomous Clock Trimming Bits — See Table 10-18 for trimming effects. The ACLKTR[5:0] value
ACLKTR[5:0] represents a signed number influencing the ACLK period time.
Table 10-18. Trimming Effect of ACLKTR
Bit
ACLKTR[5]
ACLKTR[4]
ACLKTR[3]
ACLKTR[2]
ACLKTR[1]
ACLKTR[0]
Trimming Effect
Increases period
Decreases period less than ACLKTR[5] increased it
Decreases period less than ACLKTR[4]
Decreases period less than ACLKTR[3]
Decreases period less than ACLKTR[2]
Decreases period less than ACLKTR[1]
10.3.2.16 Autonomous Periodical Interrupt Rate High and Low Register
(CPMUAPIRH / CPMUAPIRL)
The CPMUAPIRH and CPMUAPIRL registers allow the configuration of the autonomous periodical
interrupt rate.
MC9S12G Family Reference Manual, Rev.1.01
354
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.