MC9S12G Datasheet, PDF (352/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
0x02F1
7
6
5
4
3
R
0
0
0
0
0
W
Reset
0
0
0
0
0
The Reset state of LVDS and LVIF depends on the external supplied VDDA level
= Unimplemented or Reserved
2
LVDS
U
1
LVIE
0
0
LVIF
U
Figure 10-16. Low Voltage Control Register (CPMULVCTL)
Read: Anytime
Write: LVIE and LVIF are write anytime, LVDS is read only
Field
2
LVDS
1
LVIE
0
LVIF
Table 10-15. CPMULVCTL Field Descriptions
Description
Low-Voltage Detect Status Bit — This read-only status bit reflects the voltage level on VDDA. Writes have no
effect.
0 Input voltage VDDA is above level V_LVID or RPM.
1 Input voltage VDDA is below level V_LVIA and FPM.
Low-Voltage Interrupt Enable Bit
0 Interrupt request is disabled.
1 Interrupt will be requested whenever LVIF is set.
Low-Voltage Interrupt Flag — LVIF is set to 1 when LVDS status bit changes. This flag can only be cleared by
writing a 1. Writing a 0 has no effect. If enabled (LVIE = 1), LVIF causes an interrupt request.
0 No change in LVDS bit.
1 LVDS bit has changed.
10.3.2.14 Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
The CPMUAPICTL register allows the configuration of the autonomous periodical interrupt features.
0x02F2
R
W
Reset
7
6
0
APICLK
5
4
3
2
1
0
APIES
APIEA
APIFE
APIE
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-17. Autonomous Periodical Interrupt Control Register (CPMUAPICTL)
0
APIF
0
Read: Anytime
MC9S12G Family Reference Manual, Rev.1.01
352
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.