MC9S12G Datasheet, PDF (279/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Chapter 8
S12S Debug Module (S12SDBG)
Revision History
Revision Number
Date
02.00
31.JUL..2007
02.01
02.02
09.AUG..2007
10.AUG..2007
02.03
29.AUG..2007
02.04
02.05
17.OCT.2007
19.OCT.2007
02.06
22.NOV.2007
02.07
13.DEC.2007
Author
Summary of Changes
State sequencer encoding enhanced
Simultaneous TRIG and ARM setting updated
Pure PC replaced with Compressed Pure PC Mode 8.4.5.2.4
Enhanced compressed Pure PC mode description
Added CompA size & databus byte compare enhancement
DBGSCR1 encoding 1101 added.
CompA functional description improved
Swapped NDB and SZ in DBGACTL to match DBGBCTL
Reverted to final state transition priority
Table 8-33 DB byte access configuration corrected
Table 8-39 Correction
Section 8.4.5.6, “Trace Buffer Reset State Added NOTE
Section 8.5, “Application Information Added application
information
8.1 Introduction
The S12SDBG module provides an on-chip trace buffer with flexible triggering capability to allow
non-intrusive debug of application software. The S12SDBG module is optimized for S12SCPU
debugging.
Typically the S12SDBG module is used in conjunction with the S12SBDM module, whereby the user
configures the S12SDBG module for a debugging session over the BDM interface. Once configured the
S12SDBG module is armed and the device leaves BDM returning control to the user program, which is
then monitored by the S12SDBG module. Alternatively the S12SDBG module can be configured over a
serial interface using SWI routines.
8.1.1 Glossary Of Terms
COF: Change Of Flow. Change in the program flow due to a conditional branch, indexed jump or interrupt.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
279
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.