MC9S12G Datasheet, PDF (502/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Freescale’s Scalable Controller Area Network (S12MSCANV3)
16.3.2.15 MSCAN Receive Error Counter (CANRXERR)
This register reflects the status of the MSCAN receive error counter.
Module Base + 0x000E
Access: User read/write¹
7
R RXERR7
6
RXERR6
5
RXERR5
4
RXERR4
3
RXERR3
2
RXERR2
1
RXERR1
0
RXERR0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-18. MSCAN Receive Error Counter (CANRXERR)
1 _{Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)}
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
Writing to this register when in special modes can alter the MSCAN
functionality.
16.3.2.16 MSCAN Transmit Error Counter (CANTXERR)
This register reflects the status of the MSCAN transmit error counter.
Module Base + 0x000F
Access: User read/write¹
7
R TXERR7
6
TXERR6
5
TXERR5
4
TXERR4
3
TXERR3
2
TXERR2
1
TXERR1
0
TXERR0
W
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 16-19. MSCAN Transmit Error Counter (CANTXERR)
1 _{Read: Only when in sleep mode (SLPRQ = 1 and SLPAK = 1) or initialization mode (INITRQ = 1 and INITAK = 1)}
Write: Unimplemented
NOTE
Reading this register when in any other mode other than sleep or
initialization mode, may return an incorrect value. For MCUs with dual
CPUs, this may result in a CPU fault condition.
MC9S12G Family Reference Manual, Rev.1.01
502
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.