MC9S12G Datasheet, PDF (390/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B8CV2)
11.3.2.8 ATD Compare Enable Register (ATDCMPE)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x0008
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
W
CMPE[7:0]
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-10. ATD Compare Enable Register (ATDCMPE)
Table 11-17. ATDCMPE Field Descriptions
Field
Description
7–0
CMPE[7:0]
Compare Enable for Conversion Number n (n= 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion number,
NOT channel number!) — These bits enable automatic compare of conversion results individually for
conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT
register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
11.3.2.9 ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF[7:0].
Module Base + 0x000A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
0
0
0
0
0
0
0
CCF[7:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-11. ATD Status Register 2 (ATDSTAT2)
Read: Anytime
Write: Anytime, no effect
MC9S12G Family Reference Manual, Rev.1.01
390
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.