MC9S12G Datasheet, PDF (1131/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

0x00F0–0x0F7 Serial Peripheral Interface (SPI1)
R
0
0
0x00F2 SPI1BR
SPPR2 SPPR1 SPPR0
W
0x00F3
SPI1SR
R SPIF
W
0
SPTEF MODF
0
R R15
R14
R13
R12
R11
0x00F4 SPI1DRH
W T15
T14
T13
T12
T11
R R7
R6
R5
R4
R3
0x00F5 SPI1DRL
W T7
T6
T5
T4
T3
0x00F6-
0x00F7
Reserved
R
W
Detailed Register Address Map
SPR2
0
R10
T10
R2
T2
SPR1
0
R9
T9
R1
T1
SPR0
0
R8
T8
R0
T0
0x00F8–0x0FF Serial Peripheral Interface (SPI2)
Address Name
Bit 7
0x00F8
R
SPI2CR1
SPIE
W
R
0
0x00F9 SPI2CR2
W
R
0
0x00FA SPI2BR
W
0x00FB
SPI2SR
R SPIF
W
R R15
0x00FC SPI2DRH
W T15
R R7
0x00FD SPI2DRL
W T7
0x00FE-
0x00FF
Reserved
R
W
Bit 6
SPE
XFRW
SPPR2
0
Bit 5
Bit 4
Bit 3
SPTIE
MSTR
CPOL
0
SPPR1
SPTEF
MODFEN BIDIROE
0
SPPR0
MODF
0
R14
R13
R12
R11
T14
T13
T12
T11
R6
R5
R4
R3
T6
T5
T4
T3
Bit 2
CPHA
0
SPR2
0
R10
T10
R2
T2
Bit 1
SSOE
SPISWAI
SPR1
0
R9
T9
R1
T1
Bit 0
LSBFE
SPC0
SPR0
0
R8
T8
R0
T0
0x0100–0x0113 Flash Module (FTMRG)
Address
0x0100
0x0101
0x0102
0x0103
0x0104
0x0105
0x0106
Name
FCLKDIV
FSEC
FCCOBIX
Reserved
FCNFG
FERCNFG
FSTAT
Bit 7
R FDIVLD
W
R KEYEN1
W
R
0
W
R
0
W
R
CCIE
W
R
0
W
R
CCIF
W
Bit 6
FDIVLCK
KEYEN0
0
0
0
0
0
Bit 5
FDIV5
RNV5
0
0
0
0
ACCERR
Bit 4
FDIV4
RNV4
0
0
IGNSF
0
FPVIOL
Bit 3
FDIV3
RNV3
Bit 2
FDIV2
RNV2
Bit 1
FDIV1
SEC1
Bit 0
FDIV0
SEC0
0
CCOBIX2 CCOBIX1 CCOBIX0
0
0
0
0
0
0
MGBUSY
0
0
RSVD
FDFD
FSFD
DFDIE SFDIE
MGSTAT1 MGSTAT0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
1131
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.