MC9S12G Datasheet, PDF (1066/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

240 KByte Flash Module (S12FTMRG240K2V1)
NOTE
Vector addresses and their relative interrupt priority are determined at the
MCU level.
28.4.7.1 Description of Flash Interrupt Operation
The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to Section 28.3.2.5, “Flash Configuration Register
(FCNFG)”, Section 28.3.2.6, “Flash Error Configuration Register (FERCNFG)”, Section 28.3.2.7, “Flash
Status Register (FSTAT)”, and Section 28.3.2.8, “Flash Error Status Register (FERSTAT)”.
The logic used for generating the Flash module interrupts is shown in Figure 28-27.
CCIE
CCIF
Flash Command Interrupt Request
DFDIE
DFDIF
SFDIE
SFDIF
Flash Error Interrupt Request
Figure 28-27. Flash Module Interrupts Implementation
28.4.8 Wait Mode
The Flash module is not affected if the MCU enters wait mode. The Flash module can recover the MCU
from wait via the CCIF interrupt (see Section 28.4.7, “Interrupts”).
28.4.9 Stop Mode
If a Flash command is active (CCIF = 0) when the MCU requests stop mode, the current Flash operation
will be completed before the MCU is allowed to enter stop mode.
MC9S12G Family Reference Manual, Rev.1.01
1066
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.