MC9S12G Datasheet, PDF (159/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Global Address
Register Name
0x027E
PIF0AD
Table 2-20. Block Register Map (G2) (continued)
Bit 7
6
5
4
3
2
1
Bit 0
R
PIF0AD7 PIF0AD6 PIF0AD5 PIF0AD4 PIF0AD3 PIF0AD2 PIF0AD1 PIF0AD0
W
0x027F
PIF1AD
R
PIF1AD7 PIF1AD6 PIF1AD5 PIF1AD4 PIF1AD3 PIF1AD2 PIF1AD1 PIF1AD0
W
= Unimplemented or Reserved
2.4.2.3 Block Register Map (G3)
Table 2-21. Block Register Map (G3)
Global Address
Register Name
Bit 7
6
5
4
3
2
0x0000–0x0007 R
0
0
0
0
0
0
Reserved
W
0x0008
R
0
0
0
0
0
0
PORTE
W
0x0009
R
0
0
0
0
0
0
DDRE
W
0x000A–0x000B R
Non-PIM
W
Address Range
Non-PIM Address Range
0x000C
R
0
0
0
0
PUCR
W
BKPUE
PDPEE
0x000D
R
0
0
0
0
0
0
Reserved
W
0x000E–0x001B R
Non-PIM
W
Address Range
Non-PIM Address Range
0x001C
ECLKCTL
R
NECLK
W
NCLKX2
DIV16
EDIV4
EDIV3
EDIV2
0x001D
R
0
0
0
0
0
0
Reserved
W
= Unimplemented or Reserved
1
0
PE1
DDRE1
0
0
EDIV1
0
Bit 0
0
PE0
DDRE0
0
0
EDIV0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
159
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.