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MC9S12G Datasheet, PDF (174/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Port Integration Module (S12GPIMV0)
1 Read: Anytime
Write:
IRQE: Once in normal mode, anytime in special mode
IRQEN: Anytime
Table 2-34. IRQCR Register Field Descriptions
Field
Description
7
IRQE
6
IRQEN
IRQ select edge sensitive onlyâ
1 IRQ pin conï¬gured to respond only to falling edges. Falling edges on the IRQ pin are detected anytime when
IRQE=1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
0 IRQ pin conï¬gured for low level recognition
IRQ enableâ
1 IRQ pin is connected to interrupt logic
0 IRQ pin is disconnected from interrupt logic
NOTE
If the input is driven to active level (IRQ=0) a write access to set either
IRQCR[IRQEN] and IRQCR[IRQE] to 1 simultaneously or to set
IRQCR[IRQEN] to 1 when IRQCR[IRQE]=1 causes an IRQ interrupt to be
generated if the I-bit is cleared. Refer to Section 2.6.3, âEnabling IRQ
edge-sensitive modeâ.
2.4.3.14 Reserved Register
Address 0x001F
7
R
Reserved
W
Reset
x
6
Reserved
x
1 Read: Anytime
Write: Only in special mode
5
Reserved
4
Reserved
3
Reserved
2
Reserved
x
x
x
x
Figure 2-15. Reserved Register
Access: User read/write1
1
0
Reserved Reserved
x
x
These reserved registers are designed for factory test purposes only and are
not intended for general user access. Writing to these registers when in
special mode can alter the moduleâs functionality.
MC9S12G Family Reference Manual, Rev.1.01
174
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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