MC9S12G Datasheet, PDF (980/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

192 KByte Flash Module (S12FTMRG192K2V1)
CCOBIX bits are readable and writable while remaining bits read 0 and are not writable.
Table 27-12. FCCOBIX Field Descriptions
Field
Description
2–0
Common Command Register Index— The CCOBIX bits are used to select which word of the FCCOB register
CCOBIX[1:0] array is being read or written to. See Section 27.3.2.11, “Flash Common Command Object Register
(FCCOB)“,” for more details.
27.3.2.4 Flash Reserved0 Register (FRSV0)
This Flash register is reserved for factory testing.
Offset Module Base + 0x000C
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-8. Flash Reserved0 Register (FRSV0)
All bits in the FRSV0 register read 0 and are not writable.
27.3.2.5 Flash Configuration Register (FCNFG)
The FCNFG register enables the Flash command complete interrupt and forces ECC faults on Flash array
read access from the CPU.
Offset Module Base + 0x0004
R
W
Reset
7
CCIE
0
6
5
4
3
2
0
0
0
0
IGNSF
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-9. Flash Configuration Register (FCNFG)
1
FDFD
0
0
FSFD
0
CCIE, IGNSF, FDFD, and FSFD bits are readable and writable while remaining bits read 0 and are not
writable.
MC9S12G Family Reference Manual, Rev.1.01
980
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.