MC9S12G Datasheet, PDF (543/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Pulse-Width Modulator (S12PWM8B8CV2)
Table 17-4. PWMCLK Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field
Description
7-0
PCLK[7:0]
Pulse Width Channel 7-0 Clock Select
0 Clock A or B is the clock source for PWM channel 7-0, as shown in Table 17-5 and Table 17-6.
1 Clock SA or SB is the clock source for PWM channel 7-0, as shown in Table 17-5 and Table 17-6.
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK and PCLKABx bits
in PWMCLKAB (see Section 17.3.2.7, “PWM Clock A/B Select Register (PWMCLKAB)). For Channel
0, 1, 4, 5, the selection is shown in Table 17-5; For Channel 2, 3, 6, 7, the selection is shown in Table 17-6.
Table 17-5. PWM Channel 0, 1, 4, 5 Clock Source Selection
PCLKAB[0,1,4,5]
0
0
1
1
PCLK[0,1,4,5]
0
1
0
1
Clock Source Selection
Clock A
Clock SA
Clock B
Clock SB
Table 17-6. PWM Channel 2, 3, 6, 7 Clock Source Selection
PCLKAB[2,3,6,7]
0
0
1
1
PCLK[2,3,6,7]
0
1
0
1
Clock Source Selection
Clock B
Clock SB
Clock A
Clock SA
17.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
7
6
5
4
3
2
1
R
0
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
W
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 17-6. PWM Prescale Clock Select Register (PWMPRCLK)
Read: Anytime
Write: Anytime
NOTE
PCKB2–0 and PCKA2–0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
0
PCKA0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
543
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.