MC9S12G Datasheet, PDF (223/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Reference Voltage Attenuator (RVAV1)
If the attenuation is turned on the resistive divider is connected to VSSA, VRH_INT and VRL_INT are
connected to intermediate voltage levels:
VRH_INT = 0.9 * (VRH - VSSA) + VSSA
Eqn. 4-1
VRL_INT = 0.4 * (VRH - VSSA) + VSSA
Eqn. 4-2
The attenuated reference voltage difference (VRH_INT - VRL_INT) equals 50% of the input reference
voltage difference (VRH - VSSA). With reference voltage attenuation the resolution of the ADC is
improved by a factor of 2.
NOTE
In attenuation mode the maximum ADC clock is reduced. Please refer to the
conditions in appendix A “ATD Accuracy”, table “ATD Conversion
Performance 5V range, RVA enabled”.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
223
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.