MC9S12G Datasheet, PDF (283/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Address
0x0024
Name
R
DBGTBH
W
Bit 7
Bit 15
6
Bit 14
5
Bit 13
4
Bit 12
3
Bit 11
2
Bit 10
0x0025
0x0026
R
DBGTBL
W
Bit 7
R ¹ TBF
DBGCNT
W
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
CNT
R
0
0
0
0
0x0027 DBGSCRX
SC3
SC2
W
R
0
0
0
0
0
MC2
0x0027 DBGMFR
W
2 _0x0028
R
DBGACTL
SZE
SZ
TAG
BRK
RW
RWE
W
3 _0x0028
R
DBGBCTL
SZE
SZ
TAG
BRK
RW
RWE
W
4 _0x0028
R
0
DBGCCTL
W
0
TAG
BRK
RW
RWE
R
0
0
0
0
0
0
0x0029 DBGXAH
W
R
0x002A DBGXAM
Bit 15
14
13
12
11
10
W
R
0x002B DBGXAL
Bit 7
6
5
4
3
2
W
R
0x002C DBGADH
Bit 15
14
13
12
11
10
W
R
0x002D DBGADL
Bit 7
6
5
4
3
2
W
R
0x002E DBGADHM
Bit 15
14
13
12
11
10
W
R
0x002F DBGADLM
Bit 7
6
5
4
3
2
W
1 _{This bit is visible at DBGCNT[7] and DBGSR[7]}
2 _{This represents the contents if the Comparator A control register is blended into this address.}
3 _{This represents the contents if the Comparator B control register is blended into this address}
4 _{This represents the contents if the Comparator C control register is blended into this address}
Figure 8-2. Quick Reference to DBG Registers
1
Bit 9
Bit 1
Bit 0
Bit 8
Bit 0
SC1
MC1
SC0
MC0
NDB
0
0
COMPE
COMPE
COMPE
Bit 17
Bit 16
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
9
Bit 8
1
Bit 0
8.3.2 Register Descriptions
This section consists of the DBG control and trace buffer register descriptions in address order. Each
comparator has a bank of registers that are visible through an 8-byte window between 0x0028 and 0x002F
in the DBG module register address map. When ARM is set in DBGC1, the only bits in the DBG module
registers that can be written are ARM, TRIG, and COMRV[1:0]
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
283
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.