MC9S12G Datasheet, PDF (453/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC12B16CV2)
Table 14-5. External Trigger Channel Select Coding
ETRIGSEL ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0 External trigger source is
1
0
0
1
0
1
0
0
1
1
ETRIG2¹
ETRIG3¹
1
0
1
X
X
Reserved
1
1
X
X
X
Reserved
1 _{Only if ETRIG3-0 input option is available (see device specification), else ETRISEL is ignored, that means}
external trigger source is still on one of the AD channels selected by ETRIGCH3-0
14.3.2.3 ATD Control Register 2 (ATDCTL2)
Writes to this register will abort current conversion sequence.
Module Base + 0x0002
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
AFFC
5
Reserved
4
ETRIGLE
3
ETRIGP
2
ETRIGE
0
0
0
0
0
= Unimplemented or Reserved
Figure 14-5. ATD Control Register 2 (ATDCTL2)
Table 14-6. ATDCTL2 Field Descriptions
1
ASCIE
0
0
ACMPIE
0
Field
Description
6
AFFC
5
Reserved
4
ETRIGLE
3
ETRIGP
2
ETRIGE
ATD Fast Flag Clear All
0 ATD flag clearing done by write 1 to respective CCF[n] flag.
1 Changes all ATD conversion complete flags to a fast clear sequence.
For compare disabled (CMPE[n]=0) a read access to the result register will cause the associated CCF[n] flag
to clear automatically.
For compare enabled (CMPE[n]=1) a write access to the result register will cause the associated CCF[n] flag
to clear automatically.
Do not alter this bit from its reset value.It is for Manufacturer use only and can change the ATD behavior.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 14-7 for details.
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 14-7 for details.
External Trigger Mode Enable — This bit enables the external trigger on one of the AD channels or one of the
ETRIG3-0 inputs as described in Table 14-5. If the external trigger source is one of the AD channels, the digital
input buffer of this channel is enabled. The external trigger allows to synchronize the start of conversion with
external events.
0 Disable external trigger
1 Enable external trigger
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
453
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.