MC9S12G Datasheet, PDF (166/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.3 Port A Data Direction Register (DDRA)
Address 0x0002 (G1)
7
R
DDRA7
W
6
DDRA6
Reset
0
0
Address 0x0002 (G2, G3)
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-4. Port A Data Direction Register (DDRA)
Table 2-24. DDRA Register Field Descriptions
Field
7-0
DDRA
Description
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.4 Port B Data Direction Register (DDRB)
Address 0x0003 (G1)
7
R
DDRB7
W
6
DDRB6
Reset
0
0
Address 0x0003 (G2, G3)
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
Figure 2-5. Port B Data Direction Register (DDRB)
Access: User read/write¹
1
0
DDRA1
DDRA0
0
0
Access: User read only
1
0
0
0
0
0
Access: User read/write¹
1
0
DDRB1
DDRB0
0
0
Access: User read only
1
0
0
0
0
0
MC9S12G Family Reference Manual, Rev.1.01
166
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.