MC9S12G Datasheet, PDF (284/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
8.3.2.1 Debug Control Register 1 (DBGC1)
Address: 0x0020
R
W
Reset
7
ARM
0
6
5
4
3
2
0
0
0
BDM
DBGBRK
TRIG
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-3. Debug Control Register (DBGC1)
1
0
COMRV
0
0
Read: Anytime
Write: Bits 7, 1, 0 anytime
Bit 6 can be written anytime but always reads back as 0.
Bits 4:3 anytime DBG is not armed.
NOTE
When disarming the DBG by clearing ARM with software, the contents of
bits[4:3] are not affected by the write, since up until the write operation,
ARM = 1 preventing these bits from being written. These bits must be
cleared using a second write if required.
Table 8-2. DBGC1 Field Descriptions
Field
Description
7
ARM
6
TRIG
4
BDM
3
DBGBRK
Arm Bit — The ARM bit controls whether the DBG module is armed. This bit can be set and cleared by user
software and is automatically cleared on completion of a debug session, or if a breakpoint is generated with
tracing not enabled. On setting this bit the state sequencer enters State1.
0 Debugger disarmed
1 Debugger armed
Immediate Trigger Request Bit — This bit when written to 1 requests an immediate trigger independent of state
sequencer status. When tracing is complete a forced breakpoint may be generated depending upon DBGBRK
and BDM bit settings. This bit always reads back a 0. Writing a 0 to this bit has no effect. If the
DBGTCR_TSOURCE bit is clear no tracing is carried out. If tracing has already commenced using BEGIN trigger
alignment, it continues until the end of the tracing session as defined by the TALIGN bit, thus TRIG has no affect.
In secure mode tracing is disabled and writing to this bit cannot initiate a tracing session.
The session is ended by setting TRIG and ARM simultaneously.
0 Do not trigger until the state sequencer enters the Final State.
1 Trigger immediately
Background Debug Mode Enable — This bit determines if a breakpoint causes the system to enter Background
Debug Mode (BDM) or initiate a Software Interrupt (SWI). If this bit is set but the BDM is not enabled by the
ENBDM bit in the BDM module, then breakpoints default to SWI.
0 Breakpoint to Software Interrupt if BDM inactive. Otherwise no breakpoint.
1 Breakpoint to BDM, if BDM enabled. Otherwise breakpoint to SWI
S12SDBG Breakpoint Enable Bit — The DBGBRK bit controls whether the debugger will request a breakpoint
on reaching the state sequencer Final State. If tracing is enabled, the breakpoint is generated on completion
of the tracing session. If tracing is not enabled, the breakpoint is generated immediately.
0 No Breakpoint generated
1 Breakpoint generated
MC9S12G Family Reference Manual, Rev.1.01
284
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.