MC9S12G Datasheet, PDF (192/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.39 Port P Interrupt Enable Register (PIEP)
Read: Anytime
Address 0x025E (G1, G2)
7
R
PIEP7
W
Reset
0
Address 0x025E (G3)
6
PIEP6
0
5
PIEP5
0
4
PIEP4
0
3
PIEP3
0
2
PIEP2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
PIEP5
PIEP4
PIEP3
PIEP2
0
0
0
0
0
Figure 2-40. Port P Interrupt Enable Register (PIEP)
Access: User read/write¹
1
0
PIEP1
PIEP0
0
0
Access: User read/write¹
1
0
PIEP1
PIEP0
0
0
Field
7-0
PIEP
Table 2-66. PIEP Register Field Descriptions
Description
Port P interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.4.3.40 Port P Interrupt Flag Register (PIFP)
Address 0x025F (G1, G2)
7
R
PIFP7
W
Reset
0
Address 0x025F (G3)
6
PIFP6
0
5
PIFP5
0
4
PIFP4
0
3
PIFP3
0
2
PIFP2
0
7
R
0
W
Reset
0
6
5
4
3
2
0
PIFP5
PIFP4
PIFP3
PIFP2
0
0
0
0
0
Figure 2-41. Port P Interrupt Flag Register (PIFP)
Access: User read/write¹
1
0
PIFP1
PIFP0
0
0
Access: User read/write¹
1
0
PIFP1
PIFP0
0
0
MC9S12G Family Reference Manual, Rev.1.01
192
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.