MC9S12G Datasheet, PDF (409/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
Table 12-12. ATDCTL4 Field Descriptions
Field
Description
7–5
SMP[2:0]
4–0
PRS[4:0]
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0).
Table 12-13 lists the available sample time lengths.
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
is calculated as follows:
fATDCLK = _2-----×-----₍--f-P-B---R-U----S-S----+-----1-----₎
Refer to Device Specification for allowed frequency range of f_ATDCLK.
SMP2
0
0
0
0
1
1
1
1
Table 12-13. Sample Time Select
SMP1
0
0
1
1
0
0
1
1
SMP0
0
1
0
1
0
1
0
1
Sample Time
in Number of
ATD Clock Cycles
4
6
8
10
12
16
20
24
12.3.2.6 ATD Control Register 5 (ATDCTL5)
Writes to this register will abort current conversion sequence and start a new conversion sequence. If the
external trigger function is enabled (ETRIGE=1) an initial write to ATDCTL5 is required to allow starting
of a conversion sequence which will then occur on each trigger event. Start of conversion means the
beginning of the sampling phase.
Module Base + 0x0005
7
R
0
W
6
5
4
3
2
1
0
SC
SCAN
MULT
CD
CC
CB
CA
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
409
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.