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MC9S12G Datasheet, PDF (488/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Table 16-3. CANCTL0 Register Field Descriptions (continued)
Field
Description
2
WUPE3
Wake-Up Enable â This conï¬guration bit allows the MSCAN to restart from sleep mode or from power down
mode (entered from sleep) when trafï¬c on CAN is detected (see Section 16.4.5.5, âMSCAN Sleep Modeâ). This
bit must be conï¬gured before sleep mode entry for the selected function to take effect.
0 Wake-up disabled â The MSCAN ignores trafï¬c on CAN
1 Wake-up enabled â The MSCAN is able to restart
1
SLPRQ4
Sleep Mode Request â This bit requests the MSCAN to enter sleep mode, which is an internal power saving
mode (see Section 16.4.5.5, âMSCAN Sleep Modeâ). The sleep mode request is serviced when the CAN bus is
idle, i.e., the module is not receiving a message and all transmit buffers are empty. The module indicates entry
to sleep mode by setting SLPAK = 1 (see Section 16.3.2.2, âMSCAN Control Register 1 (CANCTL1)â). SLPRQ
cannot be set while the WUPIF ï¬ag is set (see Section 16.3.2.5, âMSCAN Receiver Flag Register (CANRFLG)â).
Sleep mode will be active until SLPRQ is cleared by the CPU or, depending on the setting of WUPE, the MSCAN
detects activity on the CAN bus and clears SLPRQ itself.
0 Running â The MSCAN functions normally
1 Sleep mode request â The MSCAN enters sleep mode when CAN bus idle
0
INITRQ5,6
Initialization Mode Request â When this bit is set by the CPU, the MSCAN skips to initialization mode (see
Section 16.4.4.5, âMSCAN Initialization Modeâ). Any ongoing transmission or reception is aborted and
synchronization to the CAN bus is lost. The module indicates entry to initialization mode by setting INITAK = 1
(Section 16.3.2.2, âMSCAN Control Register 1 (CANCTL1)â).
The following registers enter their hard reset state and restore their default values: CANCTL07, CANRFLG8,
CANRIER9, CANTFLG, CANTIER, CANTARQ, CANTAAK, and CANTBSEL.
The registers CANCTL1, CANBTR0, CANBTR1, CANIDAC, CANIDAR0-7, and CANIDMR0-7 can only be
written by the CPU when the MSCAN is in initialization mode (INITRQ = 1 and INITAK = 1). The values of the
error counters are not affected by initialization mode.
When this bit is cleared by the CPU, the MSCAN restarts and then tries to synchronize to the CAN bus. If the
MSCAN is not in bus-off state, it synchronizes after 11 consecutive recessive bits on the CAN bus; if the MSCAN
is in bus-off state, it continues to wait for 128 occurrences of 11 consecutive recessive bits.
Writing to other bits in CANCTL0, CANRFLG, CANRIER, CANTFLG, or CANTIER must be done only after
initialization mode is exited, which is INITRQ = 0 and INITAK = 0.
0 Normal operation
1 MSCAN in initialization mode
1 See the Bosch CAN 2.0A/B speciï¬cation for a detailed deï¬nition of transmitter and receiver states.
2 In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
CPU enters wait (CSWAI = 1) or stop mode (see Section 16.4.5.2, âOperation in Wait Modeâ and Section 16.4.5.3, âOperation
in Stop Modeâ).
3 The CPU has to make sure that the WUPE register and the WUPIE wake-up interrupt enable register (see Section 16.3.2.6,
âMSCAN Receiver Interrupt Enable Register (CANRIER)) is enabled, if the recovery mechanism from stop or wait is required.
4 The CPU cannot clear SLPRQ before the MSCAN has entered sleep mode (SLPRQ = 1 and SLPAK = 1).
5 The CPU cannot clear INITRQ before the MSCAN has entered initialization mode (INITRQ = 1 and INITAK = 1).
6 In order to protect from accidentally violating the CAN protocol, TXCAN is immediately forced to a recessive state when the
initialization mode is requested by the CPU. Thus, the recommended procedure is to bring the MSCAN into sleep mode
(SLPRQ = 1 and SLPAK = 1) before requesting initialization mode.
7 Not including WUPE, INITRQ, and SLPRQ.
8 TSTAT1 and TSTAT0 are not affected by initialization mode.
9 RSTAT1 and RSTAT0 are not affected by initialization mode.
16.3.2.2 MSCAN Control Register 1 (CANCTL1)
The CANCTL1 register provides various control bits and handshake status information of the MSCAN
module as described below.
MC9S12G Family Reference Manual, Rev.1.01
488
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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