MC9S12G Datasheet, PDF (208/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-91. PIF1AD Register Field Descriptions
Field
Description
7-0
PIF1AD
Port AD interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.5 PIM Ports - Functional Description
2.5.1 General
Each pin except BKGD can act as general-purpose I/O. In addition most pins can act as an output or input
of a peripheral module.
2.5.2 Registers
A set of configuration registers is common to all ports with exception of the ADC port (Table 2-92). All
registers can be written at any time, however a specific configuration might not become active.
Example: Selecting a pullup device. This device does not become active while the port is used as a
push-pull output.
Table 2-92. Register availability per port¹
Data
Port (Portx,
PTx)
Input
(PTIx)
Data
Direction
(DDRx)
Pull
Enable
(PERx)
Polarity Wired- Interrupt Interrupt
Select Or Mode Enable Flag
(PPSx) (WOMx) (PIEx) (PIFx)
A
yes
-
yes
-
-
-
-
B
yes
-
yes
-
-
-
-
C
yes
-
yes
yes
-
-
-
-
D
yes
-
yes
-
-
-
-
E
yes
-
yes
-
-
-
-
T
yes
yes
yes
yes
yes
-
-
-
S
yes
yes
yes
yes
yes
yes
-
-
M
yes
yes
yes
yes
yes
yes
-
-
P
yes
yes
yes
yes
yes
-
yes
yes
J
yes
yes
yes
yes
yes
-
yes
yes
AD
yes
yes
yes
yes
yes
-
yes
yes
1 _{Each cell represents one register with individual configuration bits}
MC9S12G Family Reference Manual, Rev.1.01
208
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.