MC9S12G Datasheet, PDF (193/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
1 _{Read: Anytime}
Write: Anytime, write 1 to clear
Field
7-0
PIFP
Table 2-67. PIFP Register Field Descriptions
Description
Port P interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see Section 2.5.4.2, “Pin Interrupts and Wakeup”). This can be a rising or a falling edge based on the state of the
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.4.3.41
Reserved Registers
NOTE
Addresses 0x0260-0x0261 are reserved for ACMP registers in G2 and G3
only. Refer to Section 3.6.2.1, “ACMP Control Register (ACMPC)” and
Section 3.6.2.2, “ACMP Status Register (ACMPS)”.
2.4.3.42 Port J Data Register (PTJ)
Address 0x0268 (G1, G2)
7
R
PTJ7
W
Reset
0
Address 0x0268 (G3)
6
PTJ6
0
5
PTJ5
0
4
PTJ4
0
3
PTJ3
0
2
PTJ2
0
7
6
5
4
3
2
R
0
0
0
0
PTJ3
PTJ2
W
Reset
0
0
0
0
0
0
Figure 2-42. Port J Data Register (PTJ)
1 _{Read: Anytime. The data source is depending on the data direction value.}
Write: Anytime
Access: User read/write¹
1
0
PTJ1
PTJ0
0
0
Access: User read/write¹
1
0
PTJ1
PTJ0
0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
193
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.