MC9S12G Datasheet, PDF (654/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Timer Module (TIM16B8CV3)
PTPSR[7:0]
PRE-PRESCALER
PACLK
PACLK/256
PACLK/65536
CLK[1:0]
MUX
PR[2:1:0]
PRESCALER
1
MUX
0
TCNT(hi):TCNT(lo)
16-BIT COUNTER
CHANNEL 0
16-BIT COMPARATOR
TC0
EDG0A EDG0B
CHANNEL 1
16-BIT COMPARATOR
TC1
EDG1A EDG1B
CHANNEL2
channel 7 output
compare
TCRE
CLEAR COUNTER
TE
CxI
CxF
TOF
TOI
INTERRUPT
LOGIC
TOF
C0F
EDGE
DETECT
OM:OL0
TOV0
C0F
IOC0
CH. 0 CAPTURE
IOC0 PIN
LOGIC _{CH. 0COMPARE}
IOC0 PIN
C1F
EDGE
DETECT
OM:OL1
TOV1
C1F
IOC1
CH. 1 CAPTURE
IOC1 PIN
LOGIC _{CH. 1 COMPARE}
IOC1 PIN
CHANNEL7
16-BIT COMPARATOR
TC7
EDG7A
EDG7B
C7F
EDGE
DETECT
OM:OL7
TOV7
C7F
IOC7
PAOVF
PACNT(hi):PACNT(lo)
PACLK/65536
PACLK/256
16-BIT COUNTER
MUX
PACLK
INTERRUPT
REQUEST
INTERRUPT
LOGIC
PAMOD
PEDGE
PAOVI
PAOVF
PAI
PAIF
PEDGE
PAEN
TEN
DIVIDE-BY-64
CH.7 CAPTURE
IOC7 PIN ^{PA INPUT}
LOGIC
IOC7 PIN
CH. 7 COMPARE
EDGE
DETECT
PAIF
Bus Clock
PAOVF
PAOVI
Maximum possible channels, scalable from 0 to 7.
Pulse Accumulator is available only if channel 7 exists.
Figure 20-30. Detailed Timer Block Diagram
MC9S12G Family Reference Manual, Rev.1.01
654
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.