MC9S12G Datasheet, PDF (406/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B12CV2)
Table 12-7. External Trigger Configurations
ETRIGLE
0
0
1
1
ETRIGP
0
1
0
1
External Trigger Sensitivity
Falling edge
Rising edge
Low level
High level
12.3.2.4 ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Module Base + 0x0003
R
W
Reset
7
DJM
0
6
S8C
5
S4C
4
S2C
3
S1C
2
FIFO
0
1
0
0
0
= Unimplemented or Reserved
Figure 12-6. ATD Control Register 3 (ATDCTL3)
1
FRZ1
0
0
FRZ0
0
Read: Anytime
Write: Anytime
Table 12-8. ATDCTL3 Field Descriptions
Field
Description
7
DJM
Result Register Data Justification — Result data format is always unsigned. This bit controls justification of
conversion data in the result registers.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Table 12-9 gives example ATD results for an input signal range between 0 and 5.12 Volts.
6–3
Conversion Sequence Length — These bits control the number of conversions per sequence. Table 12-10
S8C, S4C, shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
S2C, S1C to HC12 family.
MC9S12G Family Reference Manual, Rev.1.01
406
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.