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MC9S12G Datasheet, PDF (486/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Freescaleâs Scalable Controller Area Network (S12MSCANV3)
Register
Name
0x000E
CANRXERR
Bit 7
6
5
4
3
2
1
Bit 0
R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0
W
0x000F
CANTXERR
R TXERR7
W
TXERR6
TXERR5
TXERR4
TXERR3
TXERR2
TXERR1
TXERR0
0x0010â0x0013 R
CANIDAR0â3 W AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x0014â0x0017 R
CANIDMRx
W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0018â0x001B R
CANIDAR4â7 W AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
0x001Câ0x001F R
CANIDMR4â7 W
AM7
AM6
AM5
AM4
AM3
AM2
AM1
AM0
0x0020â0x002F R
CANRXFG
W
See Section 16.3.3, âProgrammerâs Model of Message Storageâ
0x0030â0x003F R
CANTXFG
W
See Section 16.3.3, âProgrammerâs Model of Message Storageâ
= Unimplemented or Reserved
Figure 16-3. MSCAN Register Summary (continued)
16.3.2 Register Descriptions
This section describes in detail all the registers and register bits in the MSCAN module. Each description
includes a standard register diagram with an associated ï¬gure number. Details of register bit and ï¬eld
function follow the register diagrams, in bit order. All bits of all registers in this module are completely
synchronous to internal clocks during a register read.
16.3.2.1 MSCAN Control Register 0 (CANCTL0)
The CANCTL0 register provides various control bits of the MSCAN module as described below.
MC9S12G Family Reference Manual, Rev.1.01
486
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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