MC9S12G Datasheet, PDF (148/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-18. Block Memory Map (0x0000-0x027F) (continued)
Port
Global
Address
Register
Access Reset Value Section/Page
AD 0x0270 PT0AD—Port AD Data Register
R/W
0x00
2.4.3.49/2-198
0x0271
0x0272
0x0273
PT1AD—Port AD Data Register
PTI0AD—Port AD Input Register
PTI1AD—Port AD Input Register
R/W
0x00
2.4.3.50/2-199
R
3
2.4.3.51/2-199
R
3
2.4.3.54/2-201
0x0274 DDR0AD—Port AD Data Direction Register
R/W
0x00
2.4.3.53/2-200
0x0275 DDR1AD—Port AD Data Direction Register
R/W
0x00
2.4.3.54/2-201
0x0276
0x0277
Reserved for RVACTL on G(A)240 and G(A)192 only
PRR1—Pin Routing Register 1⁶
R(/W)
R/W
0x00
0x00
(4.6.2.1/4-222)
2.4.3.56/2-201
0x0278 PER0AD—Port AD Pull Device Enable Register
R/W
0x00
2.4.3.57/2-203
0x0279 PER1AD—Port AD Pull Device Enable Register
R/W
0x00
2.4.3.58/2-203
0x027A PPS0AD—Port AD Polarity Select Register
R/W
0x00
2.4.3.59/2-204
0x027B PPS1AD—Port AD Polarity Select Register
R/W
0x00
2.4.3.60/2-205
0x027C PIE0AD—Port AD Interrupt Enable Register
R/W
0x00
2.4.3.61/2-205
0x027D PIE1AD—Port AD Interrupt Enable Register
R/W
0x00
2.4.3.62/2-206
0x027E PIF0AD—Port AD Interrupt Flag Register
R/W
0x00
2.4.3.63/2-207
0x027F PIF1AD—Port AD Interrupt Flag Register
R/W
0x00
2.4.3.64/2-207
1 _{Available in group G1 only. In any other case this address is reserved.}
2 _{Refer to device memory map to determine related module.}
3 _{Read always returns logic level on pins.}
4 _{Routing takes only effect if the PKGCR is set to 20 TSSOP.}
5 _{Preset by factory.}
6 _{Routing register only available on G(A)240 and G(A)192 only. Takes only effect if the PKGCR is set to 100 LQFP.}
2.4.2 Register Map
The following tables show the individual register maps of groups G1 (Table 2-19), G2 (Table 2-20) and
G3 (Table 2-21).
NOTE
To maintain SW compatibility write data to unimplemented register bits
must be zero.
MC9S12G Family Reference Manual, Rev.1.01
148
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.