MC9S12G Datasheet, PDF (201/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-80. DDR0AD Register Field Descriptions
Field
Description
7-0 Port AD data direction—
DDR0AD This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.54 Port AD Data Direction Register (DDR1AD)
Address 0x0275
7
R
DDR1AD7
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
DDR1AD6 DDR1AD5 DDR1AD4 DDR1AD3 DDR1AD2
0
0
0
0
0
Figure 2-54. Port AD Data Direction Register (DDR1AD)
Access: User read/write¹
1
0
DDR1AD1 DDR1AD0
0
0
Table 2-81. DDR1AD Register Field Descriptions
Field
Description
7-0 Port AD data direction—
DDR1AD This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
2.4.3.55
Reserved Register
NOTE
Address 0x0276 is reserved for RVA on G(A)240 and G(A)192 only. Refer
to Section 4.6.2.1, “RVA Control Register (RVACTL)”.
2.4.3.56
Pin Routing Register 1 (PRR1)
NOTE
Routing takes only effect if PKGCR is set to select the 100 LQFP package.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
201
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.