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MC9S12G Datasheet, PDF (476/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops. | |||
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Digital Analog Converter (DAC_8B5V)
15.5.4 Mode âUnbuffered DACâ
The âUnbuffered DACâ mode is selected by DACCNTL.DACM[2:0] = 0x4. During this mode the
unbuffered analog voltage from the DAC resistor network output is available on the DACU output pin. The
operational ampliï¬er is disabled and the operational ampliï¬er signals are disconnected from the AMP pins.
For decoding of the control signals see Table 15-7.
15.5.5 Mode âUnbuffered DAC with Operational Ampliï¬erâ
The âUnbuffered DAC with Operational Ampliï¬erâ mode is selected by DACCTL.DACM[2:0] = 0x5.
During this mode the DAC resistor network and the operational ampliï¬er are enabled and usable
independent from each other. The unbuffered analog voltage from the DAC resistor network output is
available on the DACU output pin.
The operational ampliï¬er is disconnected from the DAC resistor network. All required ampliï¬er signals,
AMP, AMPP and AMPM are available on the pins. The connection between the ampliï¬er output and the
negative ampliï¬er input is open. For decoding of the control signals see Table 15-7.
15.5.6 Mode âBuffered DACâ
The âBuffered DACâ mode is selected by DACCTL.DACM[2:0] = 0x7. During this is mode the DAC
resistor network and the operational ampliï¬er are enabled. The analog output voltage from the DAC
resistor network output is buffered by the operational ampliï¬er and is available on the AMP output pin.
The DAC resistor network output is disconnected from the DACU pin. For the decoding of the control
signals see Table 15-7.
15.5.7 Analog output voltage calculation
The DAC can provide an analog output voltage in two different voltage ranges:
⢠FVR = 0, reduced voltage range
The DAC generates an analog output voltage inside the range from 0.1 x (VRH - VRL) + VRL to
0.9 x (VRH-VRL) + VRL with a resolution ((VRH-VRL) x 0.8) / 256, see equation below:
analog output voltage = VOLATGE[7:0] x ((VRH-VRL) x 0.8) / 256) + 0.1 x (VRH-VRL) + VRL Eqn. 15-1
⢠FVR = 1, full voltage range
The DAC generates an analog output voltage inside the range from VRL to VRH with a resolution
(VRH-VRL) / 256, see equation below:
analog output voltage = VOLTAGE[7:0] x (VRH-VRL) / 256 +VRL
Eqn. 15-2
MC9S12G Family Reference Manual, Rev.1.01
476
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.
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