MC9S12G Datasheet, PDF (238/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12G Memory Map Controller (S12GMMCV1)
Table 5-5. DIRECT Field Descriptions
Field
7–0
DP[15:8]
Description
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct
addressing mode. These register bits form bits [15:8] of the local address (see Figure 5-6).
Bit15
Bit8 Bit7
Bit0
DP [15:8]
CPU Address [15:0]
Figure 5-6. DIRECT Address Mapping
Example 5-1. This example demonstrates usage of the Direct Addressing Mode
MOVB
#$04,DIRECT
LDY
<$12
;Set DIRECT register to 0x04. From this point on, all memory
;accesses using direct addressing mode will be in the local
;address range from 0x0400 to 0x04FF.
;Load the Y index register from 0x0412 (direct access).
5.3.2.3 MMC Control Register (MMCCTL1)
Address: 0x0013
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-7. MMC Control Register (MMCCTL1)
1
0
0
NVMRES
0
0
Read: Anytime.
Write: Anytime.
The NVMRES bit maps 16k of internal NVM resources (see Section FTMRG) to the global address space
0x04000 to 0x07FFF.
Table 5-6. MODE Field Descriptions
Field
Description
0
NVMRES
Map internal NVM resources into the global memory map
Write: Anytime
This bit maps internal NVM resources into the global address space.
0 Program flash is mapped to the global address range from 0x04000 to 0x07FFF.
1 NVM resources are mapped to the global address range from 0x04000 to 0x07FFF.
MC9S12G Family Reference Manual, Rev.1.01
238
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.