MC9S12G Datasheet, PDF (769/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

48 KByte Flash Module (S12FTMRG48K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x000D
R
0
0
0
0
0
0
0
0
FRSV2 _W
0x000E
R
0
0
0
0
0
0
0
0
FRSV3 _W
0x000F
R
0
0
0
0
0
0
0
0
FRSV4 _W
0x0010
R NV7
NV6
NV5
NV4
NV3
NV2
NV1
NV0
FOPT
W
0x0011
R
0
0
0
0
0
0
0
0
FRSV5 _W
0x0012
R
0
0
0
0
0
0
0
0
FRSV6 _W
0x0013
R
0
0
0
0
0
0
0
0
FRSV7 _W
= Unimplemented or Reserved
Figure 23-4. FTMRG48K1 Register Summary (continued)
23.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 23-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
769
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.