MC9S12G Datasheet, PDF (644/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Timer Module (TIM16B8CV3)
20.3.2.9 Timer Control Register 3/Timer Control Register 4 (TCTL3 and TCTL4)
R
W
Reset
7
EDG7B
0
6
EDG7A
5
EDG6B
4
EDG6A
3
EDG5B
2
EDG5A
0
0
0
0
0
Figure 20-16. Timer Control Register 3 (TCTL3)
1
EDG4B
0
0
EDG4A
0
R
W
Reset
7
EDG3B
0
Read: Anytime
Write: Anytime.
6
EDG3A
5
EDG2B
4
EDG2A
3
EDG1B
2
EDG1A
0
0
0
0
0
Figure 20-17. Timer Control Register 4 (TCTL4)
1
EDG0B
0
0
EDG0A
0
Table 20-11. TCTL3/TCTL4 Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero.
Field
7:0
EDGnB
EDGnA
Description
Input Capture Edge Control — These eight pairs of control bits configure the input capture edge detector
circuits.
Table 20-12. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
20.3.2.10 Timer Interrupt Enable Register (TIE)
7
6
5
4
3
2
1
0
R
C7I
C6I
C5I
C4I
C3I
C2I
C1I
C0I
W
Reset
0
0
0
0
0
0
0
0
Figure 20-18. Timer Interrupt Enable Register (TIE)
MC9S12G Family Reference Manual, Rev.1.01
644
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.