MC9S12G Datasheet, PDF(112/1160 Page) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

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MC9S12G Datasheet, PDF (112/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

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Device Overview MC9S12G-Family

Vector Address

$FFFE

$FFFE

$FFFE

$FFFE

$FFFC

$FFFA

Table 1-27. Reset Sources and Vector Locations

Reset Source

CCR

Mask

Local Enable

Power-On Reset (POR)

Low Voltage Reset (LVR)

External pin RESET

Illegal Address Reset

Clock monitor reset

COP watchdog reset

None

None

None

None

None

None

None

None

None OSCE Bit in CPMUOSC register

None CR[2:0] in CPMUCOP register

1.12.2 Interrupt Vectors

Table 1-28 lists all interrupt sources and vectors in the default order of priority. The interrupt module (see

Chapter 6, âInterrupt Module (S12SINTV1)â) provides an interrupt vector base register (IVBR) to relocate

the vectors.

Table 1-28. Interrupt Vector Locations (Sheet 1 of 2)

Vector Address1

Vector base + $F8

Vector base+ $F6

Vector base+ $F4

Vector base+ $F2

Vector base+ $F0

Interrupt Source

Unimplemented instruction trap

SWI

XIRQ

IRQ

RTI time-out interrupt

CCR

Mask

None

None

X Bit

I bit

I bit

Vector base+ $EE

TIM timer channel 0

I bit

Vector base + $EC

TIM timer channel 1

I bit

Vector base+ $EA

TIM timer channel 2

I bit

Vector base+ $E8

TIM timer channel 3

I bit

Vector base+ $E6

TIM timer channel 4

I bit

Vector base+ $E4

TIM timer channel 5

I bit

Vector base + $E2

TIM timer channel 6

I bit

Vector base+ $E0

TIM timer channel 7

I bit

Vector base+ $DE

TIM timer overï¬ow

I bit

Vector base+ $DC TIM Pulse accumulator A overï¬ow2 I bit

Vector base + $DA TIM Pulse accumulator input edge3 I bit

Vector base + $D8

SPI0

I bit

Vector base+ $D6

SCI0

I bit

Vector base + $D4

SCI1

I bit

Local Enable

None

None

None

IRQCR (IRQEN)

CPMUINT (RTIE)

TIE (C0I)

TIE (C1I)

TIE (C2I)

TIE (C3I)

TIE (C4I)

TIE (C5I)

TIE (C6I)

TIE (C7I)

TSCR2 (TOI)

PACTL (PAOVI)

PACTL (PAI)

SPI0CR1 (SPIE, SPTIE)

SCI0CR2

(TIE, TCIE, RIE, ILIE)

SCI1CR2

(TIE, TCIE, RIE, ILIE)

Wake up Wakeup

from STOP from WAIT

-

-

-

-

Yes

Yes

Yes

Yes

10.6 Interrupts

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

No

Yes

Yes

Yes

Yes

Yes

MC9S12G Family Reference Manual, Rev.1.01

112

Freescale Semiconductor

This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.

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