MC9S12G Datasheet, PDF (207/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
2.4.3.63 Port AD Interrupt Flag Register (PIF0AD)
Address 0x027E (G1, G2)
7
R
PIF0AD7
W
Reset
0
Address 0x027E (G3)
6
PIF0AD6
0
5
PIF0AD5
0
4
PIF0AD4
0
3
PIF0AD3
0
2
PIF0AD2
0
7
6
5
4
3
2
R
0
0
0
0
PIF0AD3 PIF0AD2
W
Reset
0
0
0
0
0
0
Figure 2-62. Port AD Interrupt Flag Register (PIF0AD)
1 _{Read: Anytime}
Write: Anytime, write 1 to clear
Access: User read/write¹
1
0
PIF0AD1 PIF0AD0
0
0
Access: User read/write¹
1
0
PIF0AD1 PIF0AD0
0
0
Table 2-90. PIF0AD Register Field Descriptions
Field
Description
7-0
PIF0AD
Port AD interrupt flag—
If the associated interrupt enable bit is set this flag asserts after a valid active edge was detected on the related pin
(see Section 2.4.2.1, “Block Register Map (G1)”). This can be a rising or a falling edge based on the state of the
polarity select register.
Writing a logic “1” to the corresponding bit field clears the flag.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set)
0 No active edge occurred
2.4.3.64 Port AD Interrupt Flag Register (PIF1AD)
Address 0x027F
R
W
Reset
7
PIF1AD7
0
1 _{Read: Anytime}
Write: Anytime
6
PIF1AD6
5
PIF1AD5
4
PIF1AD4
3
PIF1AD3
2
PIF1AD2
0
0
0
0
0
Figure 2-63. Port AD Interrupt Flag Register (PIF1AD)
Access: User read/write¹
1
0
PIF1AD1 PIF1AD0
0
0
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
207
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.