MC9S12G Datasheet, PDF (147/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Port Integration Module (S12GPIMV0)
Table 2-18. Block Memory Map (0x0000-0x027F) (continued)
Port
Global
Address
Register
M
0x0250 PTM—Port M Data Register
0x0251 PTIM—Port M Input Register
0x0252 DDRM—Port M Data Direction Register
0x0253 Reserved
0x0254 PERM—Port M Pull Device Enable Register
0x0255 PPSM—Port M Polarity Select Register
0x0256 WOMM—Port M Wired-Or Mode Register
0x0257 PKGCR—Package Code Register
P
0x0258 PTP—Port P Data Register
0x0259 PTIP—Port P Input Register
0x025A DDRP—Port P Data Direction Register
0x025B Reserved
0x025C PERP—Port P Pull Device Enable Register
0x025D PPSP—Port P Polarity Select Register
0x025E PIEP—Port P Interrupt Enable Register
0x025F PIFP—Port P Interrupt Flag Register
0x0260 Reserved for ACMP available in group G2 and G3
0x0261
0x0262
:
0x0266
Reserved
J
0x0268 PTJ—Port J Data Register
0x0269 PTIJ—Port J Input Register
0x026A DDRJ—Port J Data Direction Register
0x026B Reserved
0x026C PERJ—Port J Pull Device Enable Register
0x026D
0x026E
0x026F
PPSJ—Port J Polarity Select Register
PIEJ—Port J Interrupt Enable Register
PIFJ—Port J Interrupt Flag Register
Access Reset Value Section/Page
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R(/W)
R(/W)
R
0x00
3
0x00
0x00
0x00
0x00
0x00
5
0x00
3
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
2.4.3.27/2-183
2.4.3.29/2-184
2.4.3.29/2-184
2.4.3.30/2-185
2.4.3.31/2-186
2.4.3.32/2-186
2.4.3.33/2-187
2.4.3.34/2-188
2.4.3.35/2-189
2.4.3.36/2-190
2.4.3.37/2-190
2.4.3.38/2-191
2.4.3.39/2-192
2.4.3.40/2-192
(3.6.2.1/3-217)
(3.6.2.2/3-218)
R/W
0x00
2.4.3.42/2-193
R
3
2.4.3.43/2-194
R/W
0x00
2.4.3.44/2-195
R
0x00
R/W 0xFF (G1,G2) 2.4.3.45/2-195
0x0F (G3)
R/W
0x00
2.4.3.46/2-196
R/W
0x00
2.4.3.47/2-197
R/W
0x00
2.4.3.48/2-197
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
147
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.