MC9S12G Datasheet, PDF (438/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Analog-to-Digital Converter (ADC10B16CV2)
Table 13-18. ATDSTAT2 Field Descriptions
Field
Description
15–0
CCF[15:0]
Conversion Complete Flag n (n= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) (n conversion number, NOT
channel number!)— A conversion complete flag is set at the end of each conversion in a sequence. The flags
are associated with the conversion position in a sequence (and also the result register number). Therefore in
non-fifo mode, CCF[4] is set when the fifth conversion in a sequence is complete and the result is available in
result register ATDDR4; CCF[5] is set when the sixth conversion in a sequence is complete and the result is
available in ATDDR5, and so forth.
If automatic compare of conversion results is enabled (CMPE[n]=1 in ATDCMPE), the conversion complete flag
is only set if comparison with ATDDRn is true. If ACMPIE=1 a compare interrupt will be requested. In this case,
as the ATDDRn result register is used to hold the compare value, the result will not be stored there at the end of
the conversion but is lost.
A flag CCF[n] is cleared when one of the following occurs:
A) Write to ATDCTL5 (a new conversion sequence is started)
B) If AFFC=0, write “1” to CCF[n]
C) If AFFC=1 and CMPE[n]=0, read of result register ATDDRn
D) If AFFC=1 and CMPE[n]=1, write to result register ATDDRn
In case of a concurrent set and clear on CCF[n]: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) or D) will be overwritten by the set.
0 Conversion number n not completed or successfully compared
1 If (CMPE[n]=0): Conversion number n has completed. Result is ready in ATDDRn.
If (CMPE[n]=1): Compare for conversion result number n with compare value in ATDDRn, using compare
operator CMPGT[n] is true. (No result available in ATDDRn)
13.3.2.10 ATD Input Enable Register (ATDDIEN)
Module Base + 0x000C
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IEN[15:0]
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-12. ATD Input Enable Register (ATDDIEN)
Read: Anytime
Write: Anytime
Table 13-19. ATDDIEN Field Descriptions
Field
Description
15–0
IEN[15:0]
ATD Digital Input Enable on channel x (x= 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) — This bit controls
the digital input buffer from the analog input pin (ANx) to the digital data register.
0 Disable digital input buffer to ANx pin
1 Enable digital input buffer on ANx pin.
Note: Setting this bit will enable the corresponding digital input buffer continuously. If this bit is set while
simultaneously using it as an analog port, there is potentially increased power consumption because the
digital input buffer maybe in the linear region.
MC9S12G Family Reference Manual, Rev.1.01
438
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.