MC9S12G Datasheet, PDF (301/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
when the opcode is fetched from the memory, which precedes the instruction execution by an indefinite
number of cycles due to instruction pipelining. For a comparator match of an opcode at an odd address
when TAG = 0, the corresponding even address must be contained in the comparator register. Thus for an
opcode at odd address (n), the comparator register must contain address (n–1).
Once a successful comparator match has occurred, the condition that caused the original match is not
verified again on subsequent matches. Thus if a particular data value is verified at a given address, this
address may not still contain that data value when a subsequent match occurs.
Match[0, 1, 2] map directly to Comparators [A, B, C] respectively, except in range modes (see
Section 8.3.2.4, “Debug Control Register2 (DBGC2)). Comparator channel priority rules are described in
the priority section (Section 8.4.3.4, “Channel Priorities).
8.4.2.1 Single Address Comparator Match
With range comparisons disabled, the match condition is an exact equivalence of address bus with the
value stored in the comparator address registers. Further qualification of the type of access (R/W,
word/byte) and databus contents is possible, depending on comparator channel.
8.4.2.1.1 Comparator C
Comparator C offers only address and direction (R/W) comparison. The exact address is compared, thus
with the comparator address register loaded with address (n) a word access of address (n–1) also accesses
(n) but does not cause a match.
Table 8-31. Comparator C Access Considerations
Condition For Valid Match
Read and write accesses of ADDR[n]
Comp C Address RWE RW
ADDR[n]¹
0
X
Write accesses of ADDR[n]
ADDR[n]
1
0
Read accesses of ADDR[n]
ADDR[n]
1
1
1 _{A word access of ADDR[n-1] also accesses ADDR[n] but does not generate a match.}
The comparator address register must contain the exact address from the code.
Examples
LDAA ADDR[n]
STAA #$BYTE ADDR[n]
STAA #$BYTE ADDR[n]
LDAA #$BYTE ADDR[n]
8.4.2.1.2 Comparator B
Comparator B offers address, direction (R/W) and access size (word/byte) comparison. If the SZE bit is
set the access size (word or byte) is compared with the SZ bit value such that only the specified size of
access causes a match. Thus if configured for a byte access of a particular address, a word access covering
the same address does not lead to match.
Assuming the access direction is not qualified (RWE=0), for simplicity, the size access considerations are
shown in Table 8-32.
Table 8-32. Comparator B Access Size Considerations
Condition For Valid Match
Word and byte accesses of ADDR[n]
Comp B Address RWE SZE SZ8
ADDR[n]¹
0
0
X
Examples
MOVB #$BYTE ADDR[n]
MOVW #$WORD ADDR[n]
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
301
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.