MC9S12G Datasheet, PDF (286/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12S Debug Module (S12SDBG)
Table 8-5. SSF[2:0] — State Sequence Flag Bit Encoding
SSF[2:0]
000
001
010
011
100
101,110,111
Current State
State0 (disarmed)
State1
State2
State3
Final State
Reserved
8.3.2.3 Debug Trace Control Register (DBGTCR)
Address: 0x0022
7
6
5
4
3
2
1
0
R
0
0
0
TSOURCE
W
TRCMOD
0
TALIGN
Reset
0
0
0
0
0
0
0
0
Figure 8-5. Debug Trace Control Register (DBGTCR)
Read: Anytime
Write: Bit 6 only when DBG is neither secure nor armed.Bits 3,2,0 anytime the module is disarmed.
Table 8-6. DBGTCR Field Descriptions
Field
Description
6
TSOURCE
Trace Source Control Bit — The TSOURCE bit enables a tracing session given a trigger condition. If the MCU
system is secured, this bit cannot be set and tracing is inhibited.
This bit must be set to read the trace buffer.
0 Debug session without tracing requested
1 Debug session with tracing requested
3–2
TRCMOD
Trace Mode Bits — See Section 8.4.5.2, “Trace Modes for detailed Trace Mode descriptions. In Normal Mode,
change of flow information is stored. In Loop1 Mode, change of flow information is stored but redundant entries
into trace memory are inhibited. In Detail Mode, address and data for all memory and register accesses is stored.
In Compressed Pure PC mode the program counter value for each instruction executed is stored. See Table 8-7.
0
TALIGN
Trigger Align Bit — This bit controls whether the trigger is aligned to the beginning or end of a tracing session.
0 Trigger at end of stored data
1 Trigger before storing data
TRCMOD
00
01
10
11
Table 8-7. TRCMOD Trace Mode Bit Encoding
Description
Normal
Loop1
Detail
Compressed Pure PC
MC9S12G Family Reference Manual, Rev.1.01
286
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.