MC9S12G Datasheet, PDF (561/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Clock Source 7
High
PWMCNT6
Pulse-Width Modulator (S12PWM8B8CV2)
Low
PWMCNT7
Clock Source 5
Period/Duty Compare
High
PWMCNT4
Low
PWMCNT5
PWM7
Clock Source 3
Period/Duty Compare
High
PWMCNT2
Low
PWMCNT3
PWM5
Clock Source 1
Period/Duty Compare
High
PWMCNT0
Low
PWMCNT1
PWM3
Period/Duty Compare
PWM1
Maximum possible 16-bit channels
Figure 17-21. PWM 16-Bit Mode
Once concatenated mode is enabled (CONxx bits set in PWMCTL register), enabling/disabling the
corresponding 16-bit PWM channel is controlled by the low order PWMEx bit. In this case, the high order
bytes PWMEx bits have no effect and their corresponding PWM output is disabled.
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
561
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.