MC9S12G Datasheet, PDF (544/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

Pulse-Width Modulator (S12PWM8B8CV2)
Table 17-7. PWMPRCLK Field Descriptions
Field
Description
6–4
Prescaler Select for Clock B — Clock B is one of two clock sources which can be used for all channels. These
PCKB[2:0] three bits determine the rate of clock B, as shown in Table 17-8.
2–0
Prescaler Select for Clock A — Clock A is one of two clock sources which can be used for all channels. These
PCKA[2:0] three bits determine the rate of clock A, as shown in Table 17-8.
s
Table 17-8. Clock A or Clock B Prescaler Selects
PCKA/B2
0
0
0
0
1
1
1
1
PCKA/B1
0
0
1
1
0
0
1
1
PCKA/B0
0
1
0
1
0
1
0
1
Value of Clock A/B
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
17.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 17.4.2.5, “Left Aligned Outputs” and Section 17.4.2.6, “Center Aligned Outputs” for a more
detailed description of the PWM output modes.
R
W
Reset
7
CAE7
0
6
CAE6
5
CAE5
4
CAE4
3
CAE3
2
CAE2
1
CAE1
0
0
0
0
0
0
Figure 17-7. PWM Center Align Enable Register (PWMCAE)
0
CAE0
0
Read: Anytime
Write: Anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 17-9. PWMCAE Field Descriptions
Note: Bits related to available channels have functional significance. Writing to unavailable bits has no effect. Read from
unavailable bits return a zero
Field
7–0
CAE[7:0]
Description
Center Aligned Output Modes on Channels 7–0
0 Channels 7–0 operate in left aligned output mode.
1 Channels 7–0 operate in center aligned output mode.
MC9S12G Family Reference Manual, Rev.1.01
544
Freescale Semiconductor
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.