MC9S12G Datasheet, PDF (373/1160 Pages) Freescale Semiconductor, Inc – Ignores external trigger. Performs one conversion sequence and stops.

S12 Clock, Reset and Power Management Unit (S12CPMU)
Any change in PLL configuration or any other event which causes the PLL lock status to be cleared leads
to a loss of the oscillator status information as well (UPOSC=0).
Oscillator status change interrupts are locally enabled with the OSCIE bit.
NOTE
Losing the oscillator status (UPOSC=0) affects the clock configuration of
the system¹. This needs to be dealt with in application software.
10.6.1.4 Low-Voltage Interrupt (LVI)
In FPM the input voltage VDDA _{is monitored}. Whenever VDDA drops below level V_LVIA, the status bit
LVDS is set to 1. When VDDA rises above level V_LVID the status bit LVDS is cleared to 0. An interrupt,
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit
LVIE = 1.
10.6.1.5 Autonomous Periodical Interrupt (API)
The API sub-block can generate periodical interrupts independent of the clock source of the MCU. To
enable the timer, the bit APIFE needs to be set.
The API timer is either clocked by the Autonomous Clock (ACLK - trimmable internal RC oscillator) or
the Bus Clock. Timer operation will freeze when MCU clock source is selected and Bus Clock is turned
off. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is not
set.
The APIR[15:0] bits determine the interrupt period. APIR[15:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[15:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is re-started automatically again after it has set APIF.
The procedure to change APICLK or APIR[15:0] is first to clear APIFE, then write to APICLK or
APIR[15:0], and afterwards set APIFE.
The API Trimming bits APITR[5:0] must be set so the minimum period equals 0.2 ms if stable frequency
is desired.
See Table 10-18 for the trimming effect of APITR.
NOTE
The first period after enabling the counter by APIFE might be reduced by
API start up delay t_sdel.
It is possible to generate with the API a waveform at the external pin API_EXTCLK by setting APIFE and
enabling the external access with setting APIEA.
1. For details please refer to “10.4.6 System Clock Configurations”
MC9S12G Family Reference Manual, Rev.1.01
Freescale Semiconductor
373
This document is valid for the S12G96 and the S12G128 device. All information related to other devices is preliminary.